SWD protocol error

A wire-level fault occurred on the SWD/JTAG interface.

CORTEX_M_SWD_PROTOCOL_ERROR

Symptoms

  • Errors mention SWD ACK faults, parity errors or protocol failures.
  • Connection succeeds sometimes and fails other times (flaky, not consistent).
  • Problems appear only with an external probe on custom hardware, not on a dev board.

Likely causes

  • Wiring: SWDIO/SWCLK swapped, missing ground, or wires too long (jumper-wire setups above ~15 cm get marginal).
  • Signal integrity: SWD lines routed next to noisy signals, missing pull-up on SWDIO, or a target running at a very low core clock.
  • Debug clock too fast for the wiring — default SWD clocks assume short, clean connections.
  • Connector pinout mismatch: 10-pin Cortex Debug vs 20-pin ARM JTAG adapters wired incorrectly.

How to fix it

  1. Re-check the pinout

    Verify SWDIO, SWCLK, GND, VTref and NRST against the target’s debug header drawing — not memory. The 10-pin Cortex Debug connector is easy to mirror when crimping custom cables.

  2. Shorten and clean up wiring

    Keep probe-to-target wiring as short as possible, add a direct ground wire next to SWCLK, and route away from motors/switching regulators.

  3. Drop the SWD clock speed

    Lowering the adapter clock (e.g. from 4 MHz to 500 kHz–1 MHz) makes marginal links reliable and is the standard first fix for flaky custom boards.

  4. Rule out the target state

    If faults only appear after firmware boots, the firmware may be repurposing SWD pins — try connect-under-reset (see the connect timeout guide).

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